As AI infrastructure, hyperscale computing, and advanced semiconductor packaging continue to evolve, engineers are facing new challenges in high-speed interconnect performance, photonics integration, chiplet architectures, and 3D heterogeneous system design.
This industry workshop brings together experts from Keysight to explore the latest methodologies for designing, simulating, and validating next-generation electronic and photonic systems operating at 224G and beyond.
Attendees will gain practical insights into PCIe and Ethernet channel performance, electro-optical co-design workflows, wafer-level photonic IC validation, chiplet and 3DIC interconnect analysis, and early-stage architecture exploration for heterogeneous integration.
Through real-world examples and advanced simulation approaches, the workshop will highlight how engineering teams can reduce design iterations, improve system reliability, and accelerate development cycles for next-generation AI, networking, and data center applications.
Agenda
- 9:30 AM- Doors open
- 10:00 AM - Channel Performance as data rates increase. PCIe, Ethernet, and Silicon, presented by Pegah Alavi.
As PCIe and Ethernet data rates advance beyond 224G, traditional copper interconnects are reaching critical limits in signal integrity, channel reach, and power efficiency. We will discuss the limitations faced by designers as data rates increase, and some methods of mitigating them. As data rates increase, more designers have started using photonics and optics as a feasible solution. We will discuss silicon as a scalable solution for AI infrastructure, hyperscale data centers, and next-generation computing systems. Let’s dive into the challenges in latest electro-optical co-design methodologies, including high-speed interconnect modeling, package and channel simulation, signal integrity analysis, in context of the evolving PCIe, Ethernet, and photonics system development.
- 10:45 AM - Unified Photonic Design for AI-Driven Data Centers: From PIC Design to System-Level Validation, presented by Muhammad Umar Khan.
The rapid growth of AI-driven data centers is accelerating the need for advanced optical interconnects, including high-speed transceivers and Co-Packaged Optics (CPO). This seminar presents a unified photonic design workflow that connects PIC design, packaging, and system-level electro-optic verification within a single environment. Using AI data center interconnects as an example, attendees will explore end-to-end EOE simulation, photonic component optimization, packaging-aware design, and system-level validation methodologies that help improve signal integrity, design accuracy, and development efficiency for next-generation optical systems.
- 11:30 AM- Wafer-Level Photonic IC Validation for Known Good Die Qualification, presented by Kazuo Yamaguchi.
Keysight presents an integrated Photonic IC on-wafer Test Solution addressing measurement challenges of optical/electrical probing, thermal control, and measurement uncertainty. Leveraging high-bandwidth instrumentation, automation, and closed-loop workflows, the platform enables scalable, high-throughput characterization and reliable KGD (Known Good Die) screening for next-generation 800G and CPO optical interconnects.
- 12:15- Lunch
- 12:45 PM- Architecting Chiplets Right the First Time: Early-Stage 3DIC Interconnect Analysis, Presented by Pegah Alavi.
As chiplet and 3DIC adoption accelerates, engineers face growing challenges in designing and optimizing complex 3D interconnects while maintaining signal and power integrity in densely integrated systems. Traditional workflows often lead to excessive manual optimization, longer development cycles, and increased design iterations. Let’s dive into the by challenges in Signal Integrity, Power Integrity, Electromagnetic Coupling, Complex 3D Geometry Modeling, Hetegrogenous Integration, Simulation Runtime and Data Management.
- 1:30 PM- 3D Interconnect Designer, presented by Wim Aerts.
As heterogeneous integration and chiplet-based system design continue to evolve, engineers face increasing challenges in evaluating complex 2.5D and 3D interconnect architectures during the early stages of development. Decisions related to routing feasibility, grounding strategies, interface organization, and signal integrity significantly influence overall system performance, manufacturability, and development timelines. However, many of these issues are traditionally identified only after detailed layout stages, where modifications become expensive and time-consuming.
