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Keysight Design Forum 2026- Santa Clara

In-Person, Free of Charge

September 24, 2026
Delta Hotel, Santa Clara
2151 Laurelwood Rd, Santa Clara, CA 95054
9:30 AM – 4:00 PM

About This Event
For the first time in North America, Keysight is bringing together its full Design Engineering Software portfolio in a single event. Discover how connected workflows across design, simulation, validation, software quality, optical design, and engineering data management help teams accelerate innovation, improve collaboration, and reduce development risk.

Why You Should Attend
Engineering teams are under pressure to develop increasingly complex products faster and with greater confidence. Learn how our engineering workflows can help you:
·      Accelerate product development and innovation
·      Predict issues earlier in the design cycle
·      Improve collaboration across engineering teams
·      Reduce development risk and costly redesigns
·      Build an AI-ready engineering data foundation

The Forum will offer keynote presentations, technical sessions, live demonstrations, and opportunities to connect with peers and product experts around real-world engineering challenges. 

Agenda:
9:30 AM – Doors Open
9:30 AM – Keynote
10:10 AM – Design & Verification. Explore how engineering teams are addressing the challenges of AI-driven hardware development, analog design, and power optimization
10:35 AM – Computer-Aided Engineering & Multiphysics. Learn how virtual prototyping and simulation help predict electrical, thermal, and mechanical behavior earlier in the design process.
11:00 AM – Software Quality Engineering. Discover how AI-powered test automation improves software quality and validates real-world user experiences.
11:25 AM – Optical & Photonics Design. See how engineers model and optimize optical and photonic systems from concept through implementation.
11:50 AM – Engineering Data Management. Learn how connected data workflows improve collaboration, traceability, automation, and AI readiness.
12:25 PM – PowerArtist: Building Energy-Smart Chips. Learn how early RTL power analysis enables faster, more efficient chip design and prevents costly late-stage issues.
12:50 PM – Lunch & Demo Stations
1:30 PM- 4:00 PM: Breakout Session:
•The AI Hardware Challenge: Why Next-Generation Design Requires a New EDA Platform
•AI-Designed Analog Chips: From Research to Real-World Design
•PowerArtist- Building Energy‑Smart Chips: Modern RTL Power Techniques for Next‑Gen SoCs
•Testing from an End User's Perspective with Keysight
•AI-Ready Engineering Data: Preparing Semiconductor Design Teams for AI with SOS Enterprise
•Virtual Prototyping Redefined: Towards Predictive, Real-Time, and Immersive Simulations

Keysight Design Forum 2026 - Santa Clara