Accelerating Custom IC Development with SOS in Cadence Virtuoso and Synopsys Custom Compiler

As custom IC complexity grows, effective design data management inside the design cockpit becomes essential.


Join one or both of our two focused webinar sessions to discover how Keysight SOS integrates directly within Cadence Virtuoso and Synopsys Custom Compiler, enabling native version control, IP governance, and collaborative design workflows without disrupting analog and mixed signal development.


What you will learn?

In this webinar series, you’ll see how designers can:
• Manage check-in and check-out directly inside their design environment
• Create and control branches, baselines, and releases
• Maintain full traceability and reproducibility
• Reduce costly errors and re-spins
• Improve IP reuse across projects
• Accelerate time to tape out through streamlined collaboration


Who should attend? 
• CAD engineers
• Custom IC Design leads
• Engineering managers
• Custom designers using Cadence Virtuoso or Synopsys Custom Compiler


Choose your session
(you may register for one or both)

Do you have a question you would like us to address during the webinar?

Please fill in the question box on your right, and we’ll address it during the Q&A session.

Presenter

  • Pedro Pires
    Product Manager – Keysight Technologies
    Pedro Pires is a Product Leader at Keysight Technologies with deep expertise in data management, engineering productivity, and MLOps for electronic design automation (EDA). With over a decade of experience spanning product strategy, design infrastructure, and enterprise data lifecycle management, he has helped global semiconductor organizations modernize their engineering environments through scalable collaboration, governance, and process automation.

    At Keysight, Pedro leads initiatives that connect design and data platforms across global teams, defining the architecture for next-generation solutions that unify design data and enable AI readiness through sound data foundations. He holds a Master’s in Microelectronics Engineering, an MSc in Finance and Big Data, and is pursuing an Executive MBA at IESE Business School in Barcelona.

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Accelerating Custom IC Development with SOS in Cadence Virtuoso and Synopsys Custom Compiler