How To Design Advanced Package Interconnects Without Hatched Ground Simulation Bottlenecks

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As AI continues to drive chip development, advanced package and 3DIC designs increasingly rely on complex interconnect structures and hatched ground planes. While these structures are essential for manufacturability and performance, they introduce significant simulation challenges, often creating bottlenecks that slow design iteration and delay critical decisions.


In this webinar, we explore why traditional full-wave validation approaches struggle to scale for modern interconnect problems and how this impacts design timelines. We then introduce a mixed-domain design approach that enables efficient and scalable analysis of complex structures without sacrificing insight.


Building on this foundation, we demonstrate how engineers can explore interconnect design earlier in the workflow, evaluate trade-offs more effectively, and reduce late-stage risk. Using 3D Interconnect Designer, we will showcase practical workflows including 3D interconnect design with a user-defined bump map, full-stack die–PCB–die, and UCIe-focused examples.


The session concludes with a Q&A, providing actionable insights you can apply to your own design workflow.


What You Will Learn:

  • A practical approach to overcoming simulation bottlenecks caused by hatched ground planes
  • How mixed-domain modeling enables faster and scalable interconnect design process
  • A new workflow for exploring advanced package interconnects earlier in the design cycle
  • How to evaluate interconnect trade-offs before layout decisions are locked in
  • How to apply these concepts to real use cases, including chiplet (UCIe/BoW) and full-stack die–PCB–die designs


Who Should Attend?

  • Engineers designing advanced packages, chiplets, or 3DIC interconnects
  • Package designers working on interposer, substrate, or die-to-die connectivity
  • Teams facing long simulation times or limited design exploration capability
  • Engineers looking for a way to evaluate interconnect behavior earlier in the workflow

Presenters

  • Tim Wang Lee
    Signal Integrity Application Scientist  
    Chun-ting "Tim" Wang Lee, Ph.D., a Signal Integrity Application Scientist at Keysight Technologies, brings clarity to the complexities of Signal Integrity. With a Ph.D. from the University of Colorado at Boulder, his expertise goes beyond understanding how circuit board fabrication processes impact the simulation and measurement correlation. Tim's contributions to the signal integrity industry have earned him DesignCon’s 40-under-40 recognition. Known for his captivating presentations and engaging delivery style, he communicates complex concepts with clarity. Tim's goal is to empower engineers to navigate the intricacies of signal integrity with confidence.
  • Wim Aerts
    Product Owner
    Wim Aerts is the Product Owner for EM High-Speed Digital solutions at Keysight Technologies, focusing on EDA software for high-speed digital and signal integrity design. He has over 20 years of experience in hardware, FPGA, and embedded systems, with prior roles across the telecom, semiconductor, and aerospace industries.

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Webinar: How To Design Advanced Package Interconnects Without Hatched Ground Simulation Bottlenecks by DES Marketing